853 lines
36 KiB
C
853 lines
36 KiB
C
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/**
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******************************************************************************
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* @file stm32g4xx_hal_dma.h
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* @author MCD Application Team
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* @brief Header file of DMA HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32G4xx_HAL_DMA_H
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#define __STM32G4xx_HAL_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32g4xx_hal_def.h"
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/** @addtogroup STM32G4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup DMA_Exported_Types DMA Exported Types
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* @{
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*/
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/**
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* @brief DMA Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Request; /*!< Specifies the request selected for the specified channel.
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This parameter can be a value of @ref DMA_request */
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uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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from memory to memory or from peripheral to memory.
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This parameter can be a value of @ref DMA_Data_transfer_direction */
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uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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This parameter can be a value of @ref DMA_Memory_incremented_mode */
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uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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This parameter can be a value of @ref DMA_Peripheral_data_size */
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uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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This parameter can be a value of @ref DMA_Memory_data_size */
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uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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This parameter can be a value of @ref DMA_mode
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@note The circular buffer mode cannot be used if the memory-to-memory
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data transfer is configured on the selected Channel */
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uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
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This parameter can be a value of @ref DMA_Priority_level */
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} DMA_InitTypeDef;
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/**
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* @brief HAL DMA State structures definition
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*/
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typedef enum
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{
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HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
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HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
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HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
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HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
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} HAL_DMA_StateTypeDef;
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/**
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* @brief HAL DMA Error Code structure definition
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*/
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typedef enum
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{
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HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
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HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
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} HAL_DMA_LevelCompleteTypeDef;
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/**
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* @brief HAL DMA Callback ID structure definition
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*/
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typedef enum
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{
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HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
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HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
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HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
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HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
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HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
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} HAL_DMA_CallbackIDTypeDef;
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/**
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* @brief DMA handle Structure definition
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*/
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typedef struct __DMA_HandleTypeDef
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{
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DMA_Channel_TypeDef *Instance; /*!< Register base address */
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DMA_InitTypeDef Init; /*!< DMA communication parameters */
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HAL_LockTypeDef Lock; /*!< DMA locking object */
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__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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void *Parent; /*!< Parent object state */
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void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
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void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
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void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
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void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
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__IO uint32_t ErrorCode; /*!< DMA Error code */
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DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
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uint32_t ChannelIndex; /*!< DMA Channel Index */
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DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
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DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
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uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
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DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
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DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
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uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
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} DMA_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA_Exported_Constants DMA Exported Constants
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* @{
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*/
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/** @defgroup DMA_Error_Code DMA Error Code
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* @{
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*/
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#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
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#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
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#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
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#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
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#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
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#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
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#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
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/**
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* @}
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*/
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/** @defgroup DMA_request DMA request
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* @{
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*/
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#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
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#define DMA_REQUEST_GENERATOR0 1U
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#define DMA_REQUEST_GENERATOR1 2U
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#define DMA_REQUEST_GENERATOR2 3U
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#define DMA_REQUEST_GENERATOR3 4U
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#define DMA_REQUEST_ADC1 5U
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#define DMA_REQUEST_DAC1_CHANNEL1 6U
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#define DMA_REQUEST_DAC1_CHANNEL2 7U
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#define DMA_REQUEST_TIM6_UP 8U
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#define DMA_REQUEST_TIM7_UP 9U
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#define DMA_REQUEST_SPI1_RX 10U
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#define DMA_REQUEST_SPI1_TX 11U
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#define DMA_REQUEST_SPI2_RX 12U
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#define DMA_REQUEST_SPI2_TX 13U
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#define DMA_REQUEST_SPI3_RX 14U
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#define DMA_REQUEST_SPI3_TX 15U
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#define DMA_REQUEST_I2C1_RX 16U
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#define DMA_REQUEST_I2C1_TX 17U
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#define DMA_REQUEST_I2C2_RX 18U
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#define DMA_REQUEST_I2C2_TX 19U
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#define DMA_REQUEST_I2C3_RX 20U
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#define DMA_REQUEST_I2C3_TX 21U
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#if defined (I2C4)
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#define DMA_REQUEST_I2C4_RX 22U
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#define DMA_REQUEST_I2C4_TX 23U
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#endif /* I2C4 */
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#define DMA_REQUEST_USART1_RX 24U
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#define DMA_REQUEST_USART1_TX 25U
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#define DMA_REQUEST_USART2_RX 26U
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#define DMA_REQUEST_USART2_TX 27U
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#define DMA_REQUEST_USART3_RX 28U
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#define DMA_REQUEST_USART3_TX 29U
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#define DMA_REQUEST_UART4_RX 30U
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#define DMA_REQUEST_UART4_TX 31U
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#if defined (UART5)
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#define DMA_REQUEST_UART5_RX 32U
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#define DMA_REQUEST_UART5_TX 33U
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#endif /* UART5 */
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#define DMA_REQUEST_LPUART1_RX 34U
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#define DMA_REQUEST_LPUART1_TX 35U
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#define DMA_REQUEST_ADC2 36U
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#if defined (ADC3)
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#define DMA_REQUEST_ADC3 37U
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#endif /* ADC3 */
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#if defined (ADC4)
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#define DMA_REQUEST_ADC4 38U
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#endif /* ADC4 */
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#if defined (ADC5)
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#define DMA_REQUEST_ADC5 39U
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#endif /* ADC5 */
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#if defined (QUADSPI)
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#define DMA_REQUEST_QUADSPI 40U
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#endif /* QUADSPI */
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#if defined (DAC2)
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#define DMA_REQUEST_DAC2_CHANNEL1 41U
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#endif /* DAC2 */
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#define DMA_REQUEST_TIM1_CH1 42U
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#define DMA_REQUEST_TIM1_CH2 43U
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#define DMA_REQUEST_TIM1_CH3 44U
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#define DMA_REQUEST_TIM1_CH4 45U
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#define DMA_REQUEST_TIM1_UP 46U
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#define DMA_REQUEST_TIM1_TRIG 47U
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#define DMA_REQUEST_TIM1_COM 48U
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#define DMA_REQUEST_TIM8_CH1 49U
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#define DMA_REQUEST_TIM8_CH2 50U
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#define DMA_REQUEST_TIM8_CH3 51U
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#define DMA_REQUEST_TIM8_CH4 52U
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#define DMA_REQUEST_TIM8_UP 53U
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#define DMA_REQUEST_TIM8_TRIG 54U
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#define DMA_REQUEST_TIM8_COM 55U
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#define DMA_REQUEST_TIM2_CH1 56U
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#define DMA_REQUEST_TIM2_CH2 57U
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#define DMA_REQUEST_TIM2_CH3 58U
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#define DMA_REQUEST_TIM2_CH4 59U
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#define DMA_REQUEST_TIM2_UP 60U
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#define DMA_REQUEST_TIM3_CH1 61U
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#define DMA_REQUEST_TIM3_CH2 62U
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#define DMA_REQUEST_TIM3_CH3 63U
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#define DMA_REQUEST_TIM3_CH4 64U
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#define DMA_REQUEST_TIM3_UP 65U
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#define DMA_REQUEST_TIM3_TRIG 66U
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#define DMA_REQUEST_TIM4_CH1 67U
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#define DMA_REQUEST_TIM4_CH2 68U
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#define DMA_REQUEST_TIM4_CH3 69U
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#define DMA_REQUEST_TIM4_CH4 70U
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#define DMA_REQUEST_TIM4_UP 71U
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#if defined (TIM5)
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#define DMA_REQUEST_TIM5_CH1 72U
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#define DMA_REQUEST_TIM5_CH2 73U
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#define DMA_REQUEST_TIM5_CH3 74U
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#define DMA_REQUEST_TIM5_CH4 75U
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#define DMA_REQUEST_TIM5_UP 76U
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#define DMA_REQUEST_TIM5_TRIG 77U
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#endif /* TIM5 */
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#define DMA_REQUEST_TIM15_CH1 78U
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#define DMA_REQUEST_TIM15_UP 79U
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#define DMA_REQUEST_TIM15_TRIG 80U
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#define DMA_REQUEST_TIM15_COM 81U
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#define DMA_REQUEST_TIM16_CH1 82U
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#define DMA_REQUEST_TIM16_UP 83U
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#define DMA_REQUEST_TIM17_CH1 84U
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#define DMA_REQUEST_TIM17_UP 85U
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#if defined (TIM20)
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#define DMA_REQUEST_TIM20_CH1 86U
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#define DMA_REQUEST_TIM20_CH2 87U
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#define DMA_REQUEST_TIM20_CH3 88U
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#define DMA_REQUEST_TIM20_CH4 89U
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#define DMA_REQUEST_TIM20_UP 90U
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#endif /* TIM20 */
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#define DMA_REQUEST_AES_IN 91U
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#define DMA_REQUEST_AES_OUT 92U
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#if defined (TIM20)
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#define DMA_REQUEST_TIM20_TRIG 93U
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#define DMA_REQUEST_TIM20_COM 94U
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#endif /* TIM20 */
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#if defined (HRTIM1)
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#define DMA_REQUEST_HRTIM1_M 95U
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#define DMA_REQUEST_HRTIM1_A 96U
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#define DMA_REQUEST_HRTIM1_B 97U
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#define DMA_REQUEST_HRTIM1_C 98U
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#define DMA_REQUEST_HRTIM1_D 99U
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#define DMA_REQUEST_HRTIM1_E 100U
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#define DMA_REQUEST_HRTIM1_F 101U
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#endif /* HRTIM1 */
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#define DMA_REQUEST_DAC3_CHANNEL1 102U
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#define DMA_REQUEST_DAC3_CHANNEL2 103U
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#if defined (DAC4)
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#define DMA_REQUEST_DAC4_CHANNEL1 104U
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#define DMA_REQUEST_DAC4_CHANNEL2 105U
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#endif /* DAC4 */
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#if defined (SPI4)
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#define DMA_REQUEST_SPI4_RX 106U
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#define DMA_REQUEST_SPI4_TX 107U
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#endif /* SPI4 */
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#define DMA_REQUEST_SAI1_A 108U
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#define DMA_REQUEST_SAI1_B 109U
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#define DMA_REQUEST_FMAC_READ 110U
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#define DMA_REQUEST_FMAC_WRITE 111U
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#define DMA_REQUEST_CORDIC_READ 112U
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#define DMA_REQUEST_CORDIC_WRITE 113U
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#define DMA_REQUEST_UCPD1_RX 114U
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#define DMA_REQUEST_UCPD1_TX 115U
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/**
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* @}
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*/
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/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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* @{
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*/
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#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
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#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
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#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
|
||
|
|
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
|
||
|
|
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
|
||
|
|
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
|
||
|
|
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
|
||
|
|
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
|
||
|
|
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup DMA_mode DMA mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
|
||
|
|
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup DMA_Priority_level DMA Priority level
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
|
||
|
|
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
|
||
|
|
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
|
||
|
|
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_IT_TC DMA_CCR_TCIE
|
||
|
|
#define DMA_IT_HT DMA_CCR_HTIE
|
||
|
|
#define DMA_IT_TE DMA_CCR_TEIE
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define DMA_FLAG_GL1 0x00000001U
|
||
|
|
#define DMA_FLAG_TC1 0x00000002U
|
||
|
|
#define DMA_FLAG_HT1 0x00000004U
|
||
|
|
#define DMA_FLAG_TE1 0x00000008U
|
||
|
|
#define DMA_FLAG_GL2 0x00000010U
|
||
|
|
#define DMA_FLAG_TC2 0x00000020U
|
||
|
|
#define DMA_FLAG_HT2 0x00000040U
|
||
|
|
#define DMA_FLAG_TE2 0x00000080U
|
||
|
|
#define DMA_FLAG_GL3 0x00000100U
|
||
|
|
#define DMA_FLAG_TC3 0x00000200U
|
||
|
|
#define DMA_FLAG_HT3 0x00000400U
|
||
|
|
#define DMA_FLAG_TE3 0x00000800U
|
||
|
|
#define DMA_FLAG_GL4 0x00001000U
|
||
|
|
#define DMA_FLAG_TC4 0x00002000U
|
||
|
|
#define DMA_FLAG_HT4 0x00004000U
|
||
|
|
#define DMA_FLAG_TE4 0x00008000U
|
||
|
|
#define DMA_FLAG_GL5 0x00010000U
|
||
|
|
#define DMA_FLAG_TC5 0x00020000U
|
||
|
|
#define DMA_FLAG_HT5 0x00040000U
|
||
|
|
#define DMA_FLAG_TE5 0x00080000U
|
||
|
|
#define DMA_FLAG_GL6 0x00100000U
|
||
|
|
#define DMA_FLAG_TC6 0x00200000U
|
||
|
|
#define DMA_FLAG_HT6 0x00400000U
|
||
|
|
#define DMA_FLAG_TE6 0x00800000U
|
||
|
|
#if defined (DMA1_Channel7)
|
||
|
|
#define DMA_FLAG_GL7 0x01000000U
|
||
|
|
#define DMA_FLAG_TC7 0x02000000U
|
||
|
|
#define DMA_FLAG_HT7 0x04000000U
|
||
|
|
#define DMA_FLAG_TE7 0x08000000U
|
||
|
|
#endif /* DMA1_Channel7 */
|
||
|
|
#if defined (DMA1_Channel8)
|
||
|
|
#define DMA_FLAG_GL8 0x10000000U
|
||
|
|
#define DMA_FLAG_TC8 0x20000000U
|
||
|
|
#define DMA_FLAG_HT8 0x40000000U
|
||
|
|
#define DMA_FLAG_TE8 0x80000000U
|
||
|
|
#endif /* DMA1_Channel8 */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Exported macros -----------------------------------------------------------*/
|
||
|
|
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @brief Reset DMA handle state.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the specified DMA Channel.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the specified DMA Channel.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||
|
|
|
||
|
|
|
||
|
|
/* Interrupt & Flag management */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the current DMA Channel transfer complete flag.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval The specified transfer complete flag index.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#if defined (DMA1_Channel8)
|
||
|
|
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
|
||
|
|
DMA_FLAG_TC8)
|
||
|
|
#elif defined (DMA1_Channel6)
|
||
|
|
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
||
|
|
DMA_FLAG_TC6)
|
||
|
|
#endif /* DMA1_Channel8 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the current DMA Channel half transfer complete flag.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval The specified half transfer complete flag index.
|
||
|
|
*/
|
||
|
|
#if defined (DMA1_Channel8)
|
||
|
|
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
|
||
|
|
DMA_FLAG_HT8)
|
||
|
|
#elif defined (DMA1_Channel6)
|
||
|
|
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
||
|
|
DMA_FLAG_HT6)
|
||
|
|
#endif /* DMA1_Channel8 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the current DMA Channel transfer error flag.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval The specified transfer error flag index.
|
||
|
|
*/
|
||
|
|
#if defined (DMA1_Channel8)
|
||
|
|
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
|
||
|
|
DMA_FLAG_TE8)
|
||
|
|
#elif defined (DMA1_Channel6)
|
||
|
|
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
||
|
|
DMA_FLAG_TE6)
|
||
|
|
#endif /* DMA1_Channel8 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the current DMA Channel Global interrupt flag.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval The specified transfer error flag index.
|
||
|
|
*/
|
||
|
|
#if defined (DMA1_Channel8)
|
||
|
|
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
|
||
|
|
DMA_ISR_GIF8)
|
||
|
|
#elif defined (DMA1_Channel6)
|
||
|
|
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
|
||
|
|
DMA_ISR_GIF6)
|
||
|
|
#endif /* DMA1_Channel8 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get the DMA Channel pending flags.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @param __FLAG__ Get the specified flag.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA_FLAG_TCx Transfer complete flag
|
||
|
|
* @arg DMA_FLAG_HTx Half transfer complete flag
|
||
|
|
* @arg DMA_FLAG_TEx Transfer error flag
|
||
|
|
* @arg DMA_FLAG_GLx Global interrupt flag
|
||
|
|
* Where x can be from 1 to 8 to select the DMA Channel x flag.
|
||
|
|
* @retval The state of FLAG (SET or RESET).
|
||
|
|
*/
|
||
|
|
#if defined (DMA1_Channel8)
|
||
|
|
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
|
||
|
|
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
||
|
|
#elif defined (DMA1_Channel6)
|
||
|
|
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
|
||
|
|
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
||
|
|
#endif /* DMA1_Channel8 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear the DMA Channel pending flags.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @param __FLAG__ specifies the flag to clear.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA_FLAG_TCx Transfer complete flag
|
||
|
|
* @arg DMA_FLAG_HTx Half transfer complete flag
|
||
|
|
* @arg DMA_FLAG_TEx Transfer error flag
|
||
|
|
* @arg DMA_FLAG_GLx Global interrupt flag
|
||
|
|
* Where x can be from 1 to 8 to select the DMA Channel x flag.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#if defined (DMA1_Channel8)
|
||
|
|
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
|
||
|
|
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
||
|
|
#else
|
||
|
|
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
|
||
|
|
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
||
|
|
#endif /* DMA1_Channel8 */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the specified DMA Channel interrupts.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA_IT_TC Transfer complete interrupt mask
|
||
|
|
* @arg DMA_IT_HT Half transfer complete interrupt mask
|
||
|
|
* @arg DMA_IT_TE Transfer error interrupt mask
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the specified DMA Channel interrupts.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg DMA_IT_TC Transfer complete interrupt mask
|
||
|
|
* @arg DMA_IT_HT Half transfer complete interrupt mask
|
||
|
|
* @arg DMA_IT_TE Transfer error interrupt mask
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg DMA_IT_TC Transfer complete interrupt mask
|
||
|
|
* @arg DMA_IT_HT Half transfer complete interrupt mask
|
||
|
|
* @arg DMA_IT_TE Transfer error interrupt mask
|
||
|
|
* @retval The state of DMA_IT (SET or RESET).
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the number of remaining data units in the current DMA Channel transfer.
|
||
|
|
* @param __HANDLE__ DMA handle
|
||
|
|
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||
|
|
*/
|
||
|
|
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Include DMA HAL Extension module */
|
||
|
|
#include "stm32g4xx_hal_dma_ex.h"
|
||
|
|
|
||
|
|
/* Exported functions --------------------------------------------------------*/
|
||
|
|
|
||
|
|
/** @addtogroup DMA_Exported_Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup DMA_Exported_Functions_Group1
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Initialization and de-initialization functions *****************************/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||
|
|
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup DMA_Exported_Functions_Group2
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* IO operation functions *****************************************************/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
|
||
|
|
uint32_t DataLength);
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||
|
|
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
|
||
|
|
uint32_t Timeout);
|
||
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||
|
|
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||
|
|
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup DMA_Exported_Functions_Group3
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Peripheral State and Error functions ***************************************/
|
||
|
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||
|
|
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private macros ------------------------------------------------------------*/
|
||
|
|
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||
|
|
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||
|
|
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||
|
|
|
||
|
|
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
|
||
|
|
|
||
|
|
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||
|
|
((STATE) == DMA_PINC_DISABLE))
|
||
|
|
|
||
|
|
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||
|
|
((STATE) == DMA_MINC_DISABLE))
|
||
|
|
|
||
|
|
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
|
||
|
|
|
||
|
|
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||
|
|
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||
|
|
((SIZE) == DMA_PDATAALIGN_WORD))
|
||
|
|
|
||
|
|
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||
|
|
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||
|
|
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||
|
|
|
||
|
|
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||
|
|
((MODE) == DMA_CIRCULAR))
|
||
|
|
|
||
|
|
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||
|
|
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||
|
|
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||
|
|
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private functions ---------------------------------------------------------*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __STM32G4xx_HAL_DMA_H */
|
||
|
|
|