178 lines
3.1 KiB
C
178 lines
3.1 KiB
C
/**
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*********************************************************************
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*
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* @file IS66.h
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* @brief IS66 external SPI RAM driver header
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*
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* @date 2024-04-20 14:18:36
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* @author CT
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*
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* @details
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*
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*************************************************************************
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**/
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#include <stdint.h>
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#include "spi.h"
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#include "IS66.h"
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// ================
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// DEFINES
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// ================
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#define READ_CMD 0x03
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#define WRITE_CMD 0x02
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#define RESET_ENABLE 0x66
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#define RESET_CMD 0x99
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#define READ_ID_CMD 0x9F
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#define DEEP_POWER_DOWN_CMD 0xB9
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// ================
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// Module Variables
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// ================
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SPI_HandleTypeDef* m_spi;
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// ================
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// Public Functions
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// ================
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/*
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*
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*/
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uint32_t IS66_init(SPI_HandleTypeDef* hspi)
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{
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uint32_t ret = 0;
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m_spi = hspi;
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uint8_t buf[8] = {0};
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buf[0] = READ_ID_CMD;
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// Set CE low
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_RESET);
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HAL_SPI_Transmit(m_spi, buf, 4, 10);
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HAL_SPI_Receive(m_spi, buf, 8, 10);
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// Set CE high
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_SET);
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if (0x5D == buf[0])
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{
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ret = 1;
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}
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return(ret);
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}
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/*
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* Reads 4 bytes from addr
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*/
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uint32_t IS66_Read(uint32_t addr)
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{
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uint8_t buf[8] = {0};
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uint32_t data;
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buf[0] = READ_CMD;
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buf[1] = (addr & 0x00FF0000) >> 16;
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buf[2] = (addr & 0x0000FF00) >> 8;
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buf[3] = (addr & 0x000000FF);
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// Set CE low
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_RESET);
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HAL_SPI_Transmit(m_spi, buf, 4, 10);
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HAL_SPI_Receive(m_spi, buf, 4, 10);
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// Set CE high
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_SET);
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data = ((uint32_t)buf[3] << 24) + ((uint32_t)buf[2] << 16) + ((uint32_t)buf[1] << 8) + buf[0];
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return(data);
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}
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/*
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* Writes 4 bytes to addr
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*/
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uint32_t IS66_Write(uint32_t addr, uint32_t data)
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{
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uint8_t buf[8] = {0};
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buf[0] = WRITE_CMD;
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buf[1] = (addr & 0x00FF0000) >> 16;
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buf[2] = (addr & 0x0000FF00) >> 8;
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buf[3] = (addr & 0x000000FF);
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buf[4] = (data & 0x000000FF);
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buf[5] = (data & 0x0000FF00) >> 8;
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buf[6] = (data & 0x00FF0000) >> 16;
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buf[7] = (data & 0xFF000000) >> 24;
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// Set CE low
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_RESET);
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HAL_SPI_Transmit(m_spi, buf, 8, 10);
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// Set CE high
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_SET);
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return(0);
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}
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/*
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*
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*/
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void IS66_Deep_Power_Down(void)
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{
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uint8_t buf[8] = {0};
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buf[0] = DEEP_POWER_DOWN_CMD;
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// Set CE low
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_RESET);
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HAL_SPI_Transmit(m_spi, buf, 1, 10);
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// Set CE high
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_SET);
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}
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/*
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*
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*/
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void IS66_Exit_Deep_Power_Down(void)
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{
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// Set CE low
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_RESET);
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// Wait
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HAL_Delay(1);
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// Set CE high
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_SET);
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}
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/*
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*/
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void IS66_Reset(void)
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{
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uint8_t buf[2] = {RESET_ENABLE, RESET_CMD};
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// Set CE low
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_RESET);
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HAL_SPI_Transmit(m_spi, buf, 2, 10);
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// Set CE high
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HAL_GPIO_WritePin(RAM_CE_GPIO_Port, RAM_CE_Pin, GPIO_PIN_SET);
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} |